Driving method for driving electro-optical device, driving circuit, electro-optical device, and electronic equipment

ABSTRACT

A signal applied to a data line is binarized to provide a high-quality gray scale presentation. To provide eight gray scales, for example, one field is divided into seven subfields in accordance with gray scale characteristics of an electro-optical device. Pixels are turned on or off by writing a high-level or a low-level signal thereon in a first subfield. In subsequent subfields, high-level or low-level signals are written depending on the gray scale level of each pixel to control the ratio of the on period of the pixels to the off period of the pixels on one field.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a driving method for driving anelectro-optical device that performs gray scale display control throughpulse-width modulation, a driving circuit for the electro-opticaldevice, and electronic equipment.

2. Description of Related Art

Electro-optical devices, such as a liquid-crystal display deviceemploying a liquid crystal as an electro-optical material, are nowreplacing cathode ray tubes (CRTs), and are widely used as a display ofa variety of information processing apparatuses or of wall-mountedtelevision sets.

A conventional electro-optical device typically includes an elementsubstrate on which a matrix of pixel electrodes and switching elements,such as TFTs (Thin-Film Transistors), respectively connected to thepixel electrodes, are formed, an opposite substrate on which an oppositeelectrode, opposed to the pixel electrodes, is formed, and a liquidcrystal, as an electro-optical material, encapsulated between the twosubstrates. With this arrangement, when a scanning signal is applied tothe switching element through a scanning line, the switching elementbecomes conductive. When the pixel electrode is applied with an imagesignal having a voltage responsive to the gray scale thereof through adata line during the conductive state of the switching element, a chargeresponsive to the voltage of the image signal is stored in a liquidcrystal layer between the pixel electrode and the counter electrode.Even if the switching element is turned off subsequent to the storage ofthe charge, the storage of the charge is maintained in the liquidcrystal layer by capacitance of the liquid crystal itself and a storagecapacitor formed between the two substrates. When each switching elementis driven and the stored charge is controlled in accordance with thegray scale, the alignment of the liquid crystal in each pixel changes,and brightness can be controlled from pixel to pixel. A gray scaledisplay thus results.

Since a period of time during which the charge is stored in the liquidcrystal layer in each pixel is part of a scanning period, atime-division multiplex driving method becomes possible in which aplurality of pixels share the same scanning line or the same data line.In this driving method, first, a scanning line driving circuitsequentially selects the scanning lines, second, a data line drivingcircuit sequentially selects the data lines during a selection period ofthe scanning line, and third, the selected data line thus samples theimage signal having a voltage responsive to the gray scale thereof.

SUMMARY OF THE INVENTION

The image signal applied to the data line has a voltage responsive tothe gray scale thereof, i.e., is an analog signal. For this reason, theelectro-optical device requires peripheral circuits such as adigital-to-analog converter, and an operational amplifier, and theoverall cost of the device is increased. Due to nonuniformities in thecharacteristics of the digital-to-analog converter and the operationalamplifier, and resistance of a variety of lines, display nonuniformitiesarise. Presenting a high-quality image becomes difficult. Suchnonuniformities becomes pronounced particularly when a high-definitiondisplay is presented.

In view of the problems, the present invention has been developed, andit is an object of the present invention to provide an electro-opticaldevice that offers a high-quality and high-definition gray scaledisplay, a method for driving the electro-optical device, a drivingcircuit for driving the electro-optical device, and electronic equipmentincorporating the electro-optical device.

To achieve the above object, a first invention relates to a drivingmethod for driving an electro-optical device having a matrix of pixelsto display an image with gray scale, and includes the steps of dividingeach field into a plurality of subfields, and supplying each pixel witha voltage that sets the pixels to a ON state on a subfield-by-subfieldbasis or a voltage that sets the pixels to an OFF state on asubfield-by-subfield basis so that a ratio of a period of voltageapplication time to set the pixels to the ON state to a period ofvoltage application time to set the pixels to the OFF state in eachfield is responsive to the gray scale level of the pixel.

In the first invention time lengths of subfields divided from one fieldare long enough so as to feed different root-mean-square voltages to thepixels every different subfields.

A second invention relates to a driving method for driving anelectro-optical device having a matrix of pixels to display an imagewith gray scale, and includes the steps of dividing each field into aplurality of subfields, setting the pixels to an ON state or an OFFstate during a first subfield, and controlling each pixel depending onthe gray scale level of the pixel as to whether to remain in the ONstate or the OFF state of the pixels during subsequent subfields.

In accordance with the first invention and the second invention, the on(off) period of the pixel is pulse-width modulated with the gray scalelevel of the pixel during one field, and gray scale display is thuscontrolled by a root-mean-square value. In each subfield, it suffices tocommand each pixel to turn on or off, and as a command signal to eachpixel, a binary signal (i.e., a digital signal which takes only twolevels of a high level and a low level) is used. In the first inventionand the second invention, the signal applied to the pixel is a digitalsignal, and display nonuniformities due to irregularities in elementcharacteristics and wiring resistance are controlled. A high-quality andhigh-definition gray scale display thus results.

In the context of the present invention, one field refers to a period oftime required to form one raster image which is obtained by performing ahorizontal scanning and a vertical scanning respectively insynchronization with a horizontal scanning signal and a verticalscanning signal. Therefore, one frame in a non-interlace system is thustreated as one field in the context of the present invention.

In one embodiment of the first invention or the second invention, eachpixel is arranged as to correspond to an intersection where one of aplurality of scanning lines and one of a plurality of data lines cross,and is set to the ON state or to the OFF state depending on a voltagesupplied to the data line for a period during which the scanning line isapplied with a scanning signal, the scanning signal is supplied to thescanning lines on a subfield-by-subfield basis, and a binary signal forcommanding the pixel to be set to the ON state or the OFF state is fedto the data line of the pixel for a period during which the scanningline of the pixel is supplied with the scanning signal. In thisembodiment, when the scanning line is supplied with the scanning signaland when the data line, perpendicular to the scanning line, is suppliedwith the binary signal, the pixel corresponding to that intersection isturned on and off in response to the binary signal. In this embodiment,this operation is performed on all pixels.

To achieve the above object, a third embodiment relates to a drivingcircuit of an electro-optical device for driving pixels including apixel electrode corresponding to each intersection at which one of aplurality of scanning lines and one of a plurality of data lines cross,and a switching element for controlling a voltage supplied to each pixelelectrode, and the driving circuit includes a scanning line drivingcircuit for supplying the scanning line with a scanning signal thatturns on the switching element in each of a plurality of subfieldsdivided from one field, and a data line driving circuit for supplyingthe data line of the pixel with a binary signal commanding the pixel tobe set to the ON state or the OFF state for a period during which thescanning line of the pixel is supplied with the scanning signal, whereinthe binary signal is a command signal to set the pixel to the ON stateor to the OFF state so that a ratio of a period of voltage applicationtime to set the pixels to the ON state to a period of voltageapplication time to set the pixels to the OFF state in each field isresponsive to the gray scale level of the pixel.

A fourth invention relates to a driving circuit of an electro-opticaldevice for driving pixels including a pixel electrode at eachintersection at which one of a plurality of scanning lines and one of aplurality of data lines cross, and a switching element for controlling avoltage supplied to each pixel electrode, and the driving circuitincludes a scanning line driving circuit for supplying the scanning linewith a scanning signal that turns on the switching element in each of aplurality of subfields divided from one field, and a data line drivingcircuit for supplying the data line of the pixel with a binary signalfor a period during which the scanning line of the pixel is suppliedwith the scanning signal, wherein the binary signal commands the pixelsto be set to an ON state or an OFF state during a first subfield, andcommands the pixels as to whether to remain in the ON state or the OFFstate during a subsequent subfield.

Like the first and second inventions, the third and fourth inventionsapply a digital signal to each pixel, and display nonuniformities due toirregularities in element characteristics and wiring resistance arecontrolled. A high-quality and high-definition gray scale display thusresults.

In accordance with the third and fourth inventions, preferably, the dataline driving circuit further includes a shift register for sequentiallyshifting a latch pulse signal, supplied at the start of a horizontalscanning period, in response to a clock signal, a first latch circuitfor sequentially latching the binary signal in response to the shiftedsignal provided by the shift register, and a second latch circuit whichlatches the binary signal, latched by the first latch circuit, inresponse to the latch pulse signal while simultaneously outputting thelatched binary signals to the corresponding data lines. Since one fieldis divided into a plurality of subfields in this invention, a write timeto each pixel could be insufficient when a binary signal is supplied ina point at a time scanning in each subfield. With this arrangement,before the binary signal is fed to the data lines, the first latchcircuit latches in a point at a time scanning, and all latched signalsare then latched at a time by the second latch circuit in response tothe latch pulse signal that is supplied at the start of the horizontalscanning period and are then supplied to the data lines. With thisarrangement, one horizontal scanning period, which is a relatively longtime, is assured as the write time for the pixels.

With this arrangement, preferably, the first latch circuitsimultaneously latches the binary signals, which are branched into aplurality of lines from a single line, in response to the shifted signalprovided by the shift register. In this arrangement, a number of stagesof the shift register is reduced, and a period of time the first latchcircuit requires to latch the binary signals is thus reduced.

With the shift register incorporated in the data line driving circuit,the electro-optical device preferably includes a clock signal supplycontrol circuit, which stops the supply of the clock signal to the shiftregister after the scanning line driving circuit supplies all scanninglines with the scanning signal in one subfield, and restarts the supplyof the clock signal at the start of a subsequent subfield. Since theshift register typically includes a number of clocked inverters whichreceive the clock signal at the gates thereof, the shift register worksas a capacitive load if viewed from the source side of the clock signal.There is no need for operating the shift register on the data line sidefor a period from “when the scanning line driving circuit has fed thescanning signal to all scanning lines” to “when a next subfield starts”.The clock signal supply control circuit thus stops the supply of theclock signal to the shift register for this period, thereby reducing thepower consumed by the capacitive load of the shift register.

To achieve the above object, a fifth invention relates to anelectro-optical device and includes a pixel including a pixel electrodeat each intersection at which one of a plurality of scanning lines andone of a plurality of data lines cross, a switching element forcontrolling a voltage applied to each pixel electrode, and a counterelectrode arranged to be opposed to the pixel electrode, a scanning linedriving circuit for supplying the scanning line with a scanning signalthat turns on the switching element in each of a plurality of subfieldsdivided from one field, and a data line driving circuit for supplyingthe data line of the pixel with a binary signal for a period duringwhich the scanning line of the pixel is supplied with the scanningsignal, wherein the binary signal is a command signal to set the pixelsto the ON state or to the OFF state so that a ratio of a period ofvoltage application time to set the pixels to the ON state to a periodof voltage application time to set the pixels to the OFF state in eachfield is responsive to the gray scale level of the pixel.

A sixth invention relates to an electro-optical device and includes apixel including a pixel electrode at each intersection at which one of aplurality of scanning lines and one of a plurality of data lines cross,a switching element for controlling a voltage applied to each pixelelectrode, and a counter electrode arranged to be opposed to the pixelelectrode, a scanning line driving circuit for supplying the scanningline with a scanning signal that turns on the switching element in eachof a plurality of subfields divided from one field, and a data linedriving circuit for supplying the data line of the pixel with a binarysignal for a period during which the scanning line of the pixel issupplied with the scanning signal, wherein the binary signal commandsthe pixel to be set to an ON state or an OFF state during a firstsubfield, and commands the pixel as to whether to remain in the ON stateor the OFF state of the pixel during a subsequent subfield.

Like the first and second inventions, the fifth and sixth inventionsapply a digital signal to each pixel, and display nonuniformities due toirregularities in element characteristics and wiring resistance arecontrolled. A high-quality and high-definition gray scale display thusresults.

In the fifth and sixth inventions, the binary signal is preferablyshifted in level in response to the level of a voltage applied to thecounter electrode. With this arrangement, the counter electrode isbiased to one level at one time and to the other level at other times.With respect to a reference point set to an intermediate level betweenthe two levels, the voltage applied to the pixel is inverted in polaritywhen the counter electrode is shifted from the one level to the other,but the absolute values of the voltage of the pixel remains unchanged.This arrangement prevents a direct current component from being appliedto the electro-optical material encapsulated between the pixel electrodeand the counter electrode.

In one embodiment of the fifth invention or the sixth invention,preferably, an element substrate on which the pixel electrode and theswitching element are formed is fabricated of a semiconductor substrate,the scanning line driving circuit and the data line driving circuit areproduced on the element substrate, and the pixel electrode hasreflectivity. With high electron mobility of the semiconductorsubstrate, the switching element and other elements constituting adriving circuit, formed on the substrate, provide a fast response whilepermitting a compact design to be introduced. Since the semiconductorsubstrate is opaque, the electro-optical device is used as a reflectivetype.

To achieve the above object, a seventh invention relates to electronicequipment, and includes the above-referenced electro-optical device.With neither digital-to-analog converter nor operational amplifieremployed, the electro-optical device is free from the characteristics ofthe digital-to-analog converter and the operational amplifier, and theeffect of nonuniformities in wiring resistance. The electronic equipmentnot only becomes low-cost, but also presents a high-quality andhigh-definition gray scale display.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the electrical construction of anelectro-optical device of one embodiment of the present invention.

FIGS. 2(a) and 2(b) are circuit diagrams of one embodiment of a pixel ofthe electro-optical device.

FIG. 3 is a block diagram showing the construction of a data linedriving circuit in the electro-optical device.

FIG. 4(a) is a graph showing voltage-transmittance ratio characteristicsof the electro-optical device, and FIG. 4(b) is a diagram showing theconcept of a subfield in the electro-optical device.

FIGS. 5(a) and 5(b) are tables respectively listing converted content ofgray scale data of a data converter circuit in the electro-opticaldevice.

FIG. 6 is a timing diagram showing the operation of the electro-opticaldevice.

FIG. 7 is a timing diagram showing a voltage applied to a countersubstrate and a voltage applied to a pixel electrode during a field inthe electro-optical device.

FIG. 8 a block diagram showing a modification of the data line drivingcircuit of the electro-optical device.

FIG. 9 is a timing diagram showing the operation of the data linedriving circuit in accordance with the modification.

FIG. 10 is a circuit diagram showing a clock signal supply controlcircuit in a modification of the electro-optical device.

FIG. 11 is a timing diagram showing the operation of the clock signalsupply control circuit.

FIGS. 12(a) and 12(b) are tables respectively listing converted contentof gray scale data of a data converter circuit in the electro-opticaldevice.

FIG. 13 is a timing diagram showing a voltage applied to a countersubstrate and a voltage applied to a pixel electrode during a field inthe modification of the electro-optical device.

FIG. 14 is a plan view showing the construction of the electro-opticaldevice.

FIG. 15 is a sectional view showing the construction of theelectro-optical device.

FIG. 16 is a sectional view showing the construction of a projectorwhich is one example of electronic equipment incorporating theelectro-optical device.

FIG. 17 is a perspective view showing a personal computer as one exampleof electronic equipment incorporating the electro-optical device.

FIG. 18 is a perspective view showing a portable telephone as oneexample of electronic equipment incorporating the electro-opticaldevice.

REFERENCE NUMERALS

-   100 . . . Electro-optical device-   101 . . . Element substrate-   101 a . . . Display area-   102 . . . Counter substrate-   105 . . . Liquid crystal (electro-optical material)-   108 . . . Counter electrode-   112 . . . Scanning line-   114 . . . Data line-   116 . . . Transistor-   118 . . . Pixel electrode-   119 . . . Storage capacitor-   130 . . . Scanning line driving circuit-   140 . . . Data line driving circuit-   1410 . . . X shift register-   1420 . . . First latch circuit-   1430 . . . Second latch circuit-   200 . . . Timing signal generator circuit-   300 . . . Data converter circuit-   400 . . . Clock signal supply control circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The embodiments of the present invention are now discussed, referring tothe drawings. The electro-optical device of the embodiments is a liquidcrystal device employing a liquid crystal as an electro-opticalmaterial, and as will discussed later, an element substrate and acounter substrate are arranged to be opposed to each other with aconstant gap maintained therebetween, and the liquid crystal as theelectro-optical material is encapsulated therebetween. Theelectro-optical device of the embodiments employs a semiconductorsubstrate as the element substrate, and peripheral driving circuits areproduced on the element substrate together with transistors drivingpixels.

Electrical Construction

FIG. 1 is a block diagram showing the electrical construction of theelectro-optical device. As shown, a timing signal generator circuit 200generates a variety of timing signals and clock signals to be discussedlater, in response to a vertical scanning signal Vs, a horizontalscanning signal Hs, and a dot clock signal DCLK supplied by an unshowncontrol unit. First, an alternating driving signal FR, inverted inpolarity every field (every frame), is applied to the counter electrodeformed on the counter substrate. Second, a start pulse DY is a pulsesignal that is output first in each of subfields into which one field isdivided, as will be described later. Third, a clock signal CLY is asignal that defines a horizontal scanning period of a scanning side (Yside). Fourth, a latch pulse LP is a pulse signal, which is output firstin a horizontal scanning period, is output during a level transition(i.e., at a rising edge or a falling edge) of the clock signal CLY.Fifth, a clock signal CLX is a signal that defines a so-called dotclock.

A plurality of scanning lines 112 extend on a display area 101 a on theelement substrate in the X (row) direction, and a plurality of datalines 114 extend on the display area 101 a in the Y (column) direction.A matrix of pixels 110 is arranged, each pixel at an intersection of onescanning line 112 and one data line 114. For simplicity of discussion,in this embodiment, a number of total scanning lines 112 is set to be n,and a number of total data lines 114 is set to be n (each of m and n isan integer greater than 1). The present invention is discussed inconnection with a matrix-type display having a matrix of m rows by ncolumns, but this is not intended to limit the present invention to thisarrangement.

A specific construction of the pixel 110 is shown in FIG. 2(a). In thisconstruction, a (MOSFET) transistor 116 is configured with the gatethereof connected to the scanning line 112, with the source thereofconnected to the data line 114, and the drain thereof connected to thepixel electrode 118, and a liquid crystal 105 as an electro-opticalmaterial is encapsulated between pixel electrodes 118 and a counterelectrode 108, thereby forming a liquid-crystal layer. As will bediscussed later, the counter electrode 108 is a transparent electrodethat fully covers the counter substrate in a manner such that thecounter electrode 108 is opposed to the pixel electrodes 118.

In typical electro-optical devices, the counter electrode 108 ismaintained at a constant voltage, but in the electro-optical device ofthis embodiment, the alternating driving signal FR is applied to invertthe polarity of the counter electrode 108 every field. A storagecapacitor 119 is formed between the pixel electrode 118 and groundpotential GND, thereby preventing leakage of charge stored in theliquid-crystal layer.

Since the arrangement shown in FIG. 2(a) employs a single channel typeas the transistor 116, the effect of an offset voltage needs to beconsidered to compensate for a drop in a voltage applied to the pixelelectrode 118 caused by a parasitic capacitor formed between the gateand the drain of the transistor 116. If the pixel includes a P-channeltransistor and an N-channel transistor configured in a complementaryfashion as shown in FIG. 2(b), the effect of the offset voltage iscanceled out. However, since the complementary construction requiresthat voltages mutually opposite in phase be supplied as the scanningsignal, a single pixel 110 needs two scanning lines 112 a and 112 b.

The construction of the pixel is not limited to the ones shown in FIG.2(a) and FIG. 2(b). A memory cell, such as an SRAM, is formed in eachpixel using a transistor and a resistor, and the pixel may be thuscontrolled to an ON state or an OFF state in response to the data of ahigh level or a low level written onto the memory cell. Such anarrangement advantageously eliminates the need for addressing all pixelson a subfield by subfield basis as will be discussed later.Specifically, it suffices to supply a scanning signal to a scanning linewhich is connected to the pixel having data which need to be updated inthe memory thereof, rather than supplying the scanning signal to allscanning lines.

Returning to FIG. 1, a scanning line driving circuit 130 is a so-calledY shift register, and transfers the start pulse DY, which is suppliedfirst in a subfield, to the scanning lines 112 as scanning signals G1,G2, G3, . . . , Gm in response to the clock signal CLY.

A data line driving circuit 140 sequentially latches n binary signalsDs, a number of which equals the number of the data lines 114, duringone horizontal scanning period, and then respectively supplies latcheddata signals d1, d2, d3, . . . , dn to the corresponding data lines 114at a time during a next horizontal scanning period. The specificconstruction of the data line driving circuit 140 is shown in FIG. 3.Specifically, the data line driving circuit 140 includes an X shiftregister 1410, a first latch circuit 1420, and a second latch circuit1430. The X shift register 1410 transfers the latch pulse LP, which issupplied at the start of the horizontal scanning period, in response tothe clock signal CLX, thereby sequentially supplying latch signals S1,S2, S3, . . . , Sn. The first latch circuit 1420 sequentially latchesthe binary signal Ds at the falling edges of the latch signals S1, S2,S3, . . . , Sn. The second latch circuit 1430 simultaneously latches thebinary signals Ds, latched by the first latch circuit 1420, at thefalling edge of the latch pulse LP, while feeding data signals d1, d2,d3, . . . , dn to the respective data lines 114.

Before discussing the data converter circuit 300, the concept of thesubfield in the electro-optical device of this embodiment is discussed.The relationship between the voltage applied to the liquid-crystal layerand a relative transmittance (or reflectance) ratio of theliquid-crystal layer is something like the one shown in FIG. 4(a) in anormally-black mode which presents a black display with no voltageapplied in the liquid-crystal device employing a liquid crystal as anelectro-optical material. The relative transmittance ratio refers to theone normalized with the minimum and the maximum of transmitted lightquantity respectively set to zero % and 100%. Referring to FIG. 4(a),the transmittance ratio of the liquid-crystal device is zero % when thevoltage applied to the liquid-crystal layer is smaller than a thresholdvoltage VTH1. The transmittance ratio increases nonlinearly with theapplied voltage when the applied voltage is not lower than the thresholdvoltage VTH1 but not higher than a saturation voltage VTH2 (=V7). Whenthe applied voltage is higher than the saturation voltage VTH2, thetransmittance ratio stays at a constant regardless of the appliedvoltage. When defining the transmittance (reflectance) ratio of theliquid-crystal device, a pair of polarizer means or a single polarizermeans is accounted for.

It is assumed that the electro-optical device of this embodimentpresents an eight-gray scale display, and that gray scale (shading) datarepresented by three bits indicates a transmittance ratio thereof. Inthis case, let V0-V7 represent voltages applied to the liquid-crystallayer at respective transmittance ratios. Conventionally, these voltagesV0-V7 are directly applied to the liquid-crystal layer. At voltagesV1-V6 corresponding to intermediate gray scales, nonuniformities arelikely to occur between pixels because of the characteristics of analogcircuits, such as a digital-to-analog converter and an operationalamplifier, and variations in wiring resistances. An electro-opticaldevice having such a conventional construction has difficulty in thepresentation of a high-quality and high-definition gray scale display.

First, the electro-optical device of this embodiment uses only twovoltages V0 (=0) and V7 to be applied to the liquid-crystal layer. Withthis arrangement, when the voltage V0 is applied to the liquid-crystallayer throughout one field, the transmittance ratio becomes zero %, andwhen the voltage V7 is applied, the transmittance ratio becomes 100%.Within one field, a ratio of a period during which the voltage V0 isapplied to the liquid-crystal layer to a period during which the voltageV7 is applied to the liquid-crystal layer is controlled so that aroot-mean-square voltage applied to the liquid-crystal layer ranges fromV1 through V6. In this way, the gray scale display corresponding to therespective voltage is thus presented. Second, the electro-optical deviceof this embodiment divides one field into seven segments as shown inFIG. 4(b) to delimit the period during which the voltage V0 is appliedto the liquid-crystal layer from the period during which the voltage V7is applied to the liquid-crystal layer. The seven segments thusdelimited are designated subfields Sf1-Sf7 for convenience.

Third, the electro-optical device of this embodiment writes the voltageV7 or the voltage V0 to the pixel electrode 118 in accordance with thegray scale data for each of the subfields Sf1-Sf7. For instance, whenthe gray scale data is (001) (i.e., a gray scale display is presentedwith a pixel transmittance ratio of 14.3%) and when the voltage of thepixel electrode 118 is V0, the writing of the pixel is performed so thatthe voltage of the pixel electrode 118 at the pixel is the voltage V7 atthe subfield Sf1 within one field (1f), and that the voltage of thepixel electrode 118 is the voltage V0 at the remaining subfieldsSf2-Sf7. The root-mean-square voltage is here determined by averagingsquared instantaneous voltage values over one period (one field) and bycalculating the square root of the averaged value. If the subfield Sf1is set to be a length of (V1/V7)² within one field (1f), theroot-mean-square value of the voltage applied to the liquid-crystallayer through the writing during one field (1f) becomes V1.

For example, when the gray scale data is (010) (i.e., a gray scaledisplay is presented with a pixel transmittance ratio of 28.6%), andwhen the voltage of the counter electrode 108 is V0, the writing of thepixel is performed so that the voltage of the pixel electrode 118 at thepixel is the voltage V7 at the subfields Sf1 and Sf2 within one field(1f), and that the voltage of the pixel electrode 118 is the voltage V0at the remaining subfields Sf3-Sf7. If the subfields Sf1 and Sf2 are setto be a length of (V2/V7)² within one field (1f), the root-mean-squarevalue of the voltage applied to the liquid-crystal layer through thewriting during one field (1f) becomes V2. Since the subfield Sf1 is setto be (V1/V7)² as already discussed, the subfield Sf2 is set to be(V2/V7)²−(V1/V7)².

Similarly, when the gray scale data is (011) (i.e., a gray scale displayis presented with a pixel transmittance ratio of 42.9%), and when thevoltage of the counter electrode 108 is V0, the writing of the pixel isperformed so that the voltage of the pixel electrode 118 at the pixel isthe voltage V7 at the subfields Sf1-Sf3 within one field (1f), and thatthe voltage of the pixel electrode 118 is the voltage V0 at theremaining subfields Sf4-Sf7. If the subfields Sf1-Sf3 are set to be alength of (V3/V7)² within one field (1f), the root-mean-square value ofthe voltage applied to the liquid-crystal layer through the writingduring one field (1f) becomes V3. Since the subfields Sf1-Sf2 are set tobe (V2/V7)² as already discussed, the subfield Sf3 is set to be(V3/V7)²−(V2/V7)².

The segments of the remaining subfields Sf4-Sf6 are similarlydetermined. Finally, the subfield Sf7 is set to be a segment of(V7N7)²−(V6/V7)². A similar writing process is performed for theremaining gray scale data.

The subfields Sf1-Sf7 are thus determined. When the writingcorresponding to the gray scale data is performed, the gray scaledisplay corresponding to each transmittance ratio becomes possible eventhough the voltages applied to the liquid-crystal layer are only V0 andV7. For convenience of explanation, a logical amplitude of the appliedvoltage is so set that the voltage V7 has a high level and that thevoltage V0 has a low level.

The gray scale data for each pixel needs to be converted in one way oranother to write a high level or a low level in accordance with grayscales during each of the subfields Sf1-Sf7. The data converter circuit300 shown in FIG. 1 does this conversion. Specifically, the dataconverter circuit 300 converts three-bit gray scale data D0-D2, for eachpixel and supplied in synchronization with the vertical scanning signalVs, the horizontal scanning signal Hs, and the dot clock signal DCLK,into binary signals Ds for each of the subfields Sf1-Sf7.

The data converter circuit 300 needs an arrangement which identifies asubfield within one field. Such an arrangement works to identify thesubfield in the following way. Specifically, the data converter circuit300 may include a 3-bit counter for counting the clock signal CLY withan initial value “1” preset by the start pulse DY as an enable signal.In other words, a septinary counter for counting the start pulse DY isarranged, and a current subfield is identified by referencing the countof the counter.

Since this embodiment employs the alternating driving method, thevoltage of the counter electrode 108 is inverted in polarity every fieldby the alternating driving signal FR. The data converter circuit 300 mayinclude a counter which counts the start pulse DY while resetting thecount thereof at the level transition (the rising edge or the fallingedge) of the alternating driving signal FR. The current subfield is thusidentified by referencing the count of the counter.

Furthermore, the data converter circuit 300 needs to convert the grayscale data D0-D2 into the binary signals Ds in response to the level ofthe alternating driving signal FR. Specifically, the data convertercircuit 300 outputs the binary signals Ds corresponding to the grayscale data D0-D2 as listed in FIG. 5(a) when the alternating drivingsignal FR is at a low level. The data converter circuit 300 outputs thebinary signals Ds as listed in FIG. 5(b) when the alternating drivingsignal FR is at a high level.

Since the binary signals Ds need to be output in synchronization withthe operation of the scanning line driving circuit 130 and the data linedriving circuit 140, the data converter circuit 300 receives the startpulse DY, the clock signal CLY synchronized with the horizontalscanning, the latch pulse LP that defines the start of the horizontalscanning, and the clock signal CLX corresponding to the dot clocksignal. As discussed above, after the first latch circuit 1420 latchesthe binary signal in a point at a time scanning in one horizontalscanning period in the data line driving circuit 140, the second latchcircuit 1430 simultaneously latches the data latched by the first latchcircuit 1420 in response to the latch pulse LP, thereby simultaneouslyfeeding the data signals d1, d2, d3, . . . , dn to the data lines 114.For this reason, the data converter circuit 300 is designed to outputthe binary signals Ds at a timing which is in advance of the operationof the scanning line driving circuit 130 and the data line drivingcircuit 140 by one horizontal scanning period.

In the above embodiment, the scanning line driving circuit 130 and thedata line driving circuit 140 (or one of these circuits) are preferablyfabricated of transistors which are produced together with thetransistors 116 within the pixels 110 on the element substrate. When theelement substrate is a semiconductor substrate, the transistor may be aMOS transistor. When the element substrate is an insulator substratesuch as a glass substrate, the transistor may be a thin-film transistor.

Operation

The operation of the electro-optical device of the above embodiment isnow discussed. FIG. 6 is a timing diagram showing the operation of theelectro-optical device.

The alternating driving signal FR, shifted in level every field (1f), isapplied to the counter electrode 108. The start pulse DY is supplied atthe start of any of the subfields into which one field (1f) is dividedand which have lengths responsive to the magnitudes of the voltagesV2−V6 that define the transmittance ratios at the gray scales.

When the start pulse DY for defining the start of the subfield Sf1 issupplied in one field (1f) with the alternating driving signal FR at alow level, the scanning signals G1, G2, G3, . . . , Gm are sequentiallyoutput for a period (1 Va) in response to the clock signal CLY in thescanning line driving circuit 130 (see FIG. 1). The period (1 Va) is setto be shorter in length than the shortest subfield.

The scanning signals G1, G2, G3, . . . , Gm have respectively a pulsewidth equal to half the period of the clock signal CLY. The scanningsignal G1, corresponding to a first scanning line 112 from the top, isoutput with at least a delay of half the period of the clock signal CLYfrom the rising edge of the clock signal CLY subsequent to the supply ofthe start pulse DY. One shot (G0) of the latch pulse LP is fed to thedata line driving circuit 140 from the supply of the start pulse DY atthe start of a subfield to the output of the scanning signal G1.

The supply of the one shot (G0) of the latch pulse LP is now considered.When the one shot (G0) of the latch pulse LP is supplied to the dataline driving circuit 140, the data line driving circuit 140 (see FIG. 3)transfers the one shot (G0) therewithin in synchronization with theclock signal CLX, thereby sequentially outputting the latch signals S1,S2, S3, . . . , Sn for the horizontal scanning period (1H). Each of thelatch signals S1, S2, S3, . . . , Sn has a pulse width equal to half theperiod of the clock signal CLX.

At the falling edge of the latch signal S1, the first latch circuit 1420shown in FIG. 3 latches the binary data Ds to the pixel 110 at anintersection of the first scanning line 112 from the top and the firstdata line 114 from the left. At the falling edge of the latch signal S2,the first latch circuit 1420 latches the binary data Ds to the pixel 110at an intersection of the first scanning line 112 from the top and thesecond data line 114 from the left. Similarly, the first latch circuit1420 latches the binary signal Ds to the pixel 110 at an intersection ofthe first scanning line 112 for the top and the n-th data line 114 fromthe left.

In this way, the first latch circuit 1420 sequentially latches thebinary signals Ds for pixels of one row that intersect the firstscanning line 112 from the top as shown in FIG. 1, in a point at a timescanning. The data converter circuit 300 converts and outputs the grayscale data D0-D2 for the pixels into the binary signals Ds insynchronization with the latching of the first latch circuit 1420. Sincethe alternating driving signal FR is here at a low level, the tablelisted in FIG. 5(a) is referenced, and the binary signals Dscorresponding to the subfield Sf1 are output in response to the grayscale data D0-D2.

When the scanning signal G1 is output with the clock signal CLY falling,the first scanning line 112 from the top is selected. As a result, thetransistors 116 of the pixels 110 intersecting the scanning line 112 areall turned on. In response to the falling edge of the clock signal CLY,the latch pulse LP is output. At the timing of the falling edge of thelatch pulse LP, the second latch circuit 1430 simultaneously feeds thebinary signals Ds, which have been sequentially latched by the firstlatch circuit 1420 in a point at a time scanning, to the correspondingdata lines 114 as the data signals d1, d2, d3, . . . , dn. At the firstrow of pixels 110 from the top, the writing of the data signals d1, d2,d3, . . . , dn is simultaneously performed.

In parallel with this writing, the binary signals Ds for a row of pixelsintersecting the second scanning line 112 from the top shown in FIG. 1are sequentially latched in a point at a time scanning by the firstlatch circuit 1420.

A similar step is repeated until the scanning signal Gm is output to them-th scanning line 112. Specifically, during one horizontal scanningperiod (H) within which a scanning signal G1 (i is an integer satisfyingthe condition of 1≦i≦m) is output, the electro-optical device performsin parallel both the writing of data signals d1-dn to an i-th row ofpixels 110 corresponding to an i-th scanning line 112 and the successivelatching of the binary signals Ds in a point at a time scanning for onerow of pixels 112 corresponding to an (i+1)-th scanning line 112. Thedata written on the pixels 110 is held until a next writing during anext subfield Sf2.

A similar operation is repeated each time the start pulse DY definingthe start of the subfield is supplied. The data converter circuit 300(see FIG. 1) references the corresponding subfield of the subfieldsSf1-Sf7 when converting the gray scale data D0-D2 to the binary signalsDs.

When the alternating driving signal FR is level shifted to a high levelone field later, a similar operation is also repeated in each subfield.In this case, however, the table listed in FIG. 5(b) is referenced inthe conversion of the gray scale data D0-D2 to the binary signals Ds.

The voltage applied to the liquid-crystal layer in the pixel 110 in theabove operation is now discussed. FIG. 7 is a timing diagram showing thegray scale data, and the voltage applied to the pixel electrode 118 inthe pixel 110.

When the gray scale data D0-D2 at one pixel is (000) with thealternating driving signal FR at a low level, the conversion of the grayscale data is performed according to the table listed in FIG. 5(a). Alow level is written on the pixel electrode 118 at that pixel throughoutone field (1f) as shown in FIG. 7. Since the low level is the voltageV0, the root-mean-square voltage applied to the liquid-crystal layerbecomes V0. The transmittance ratio of that pixel becomes 0% inassociation with the gray scale data (000).

When the gray scale data D0-D2 at one pixel is (100) with thealternating driving signal FR at a low level, the conversion of the grayscale data is performed according to the table listed in FIG. 5(a).Referring to FIG. 7, on the pixel electrode 118 at that pixel, a highlevel is written during subfields Sf1-Sf4 and a low level is writtenduring subsequent subfields Sf5-Sf7. The ratio of the period of thesubfields Sf1-Sf4 to the one field (1f) is (V4/V7)², and the voltage V7,which is at a high level, is written throughout this period, and theroot-mean-square value of the voltage applied to the pixel electrode 118of the pixel in one field becomes V4. The transmittance ratio of thepixel is thus 57.1% corresponding to the gray scale data of (100).Further discussion about the remaining gray scale data is omitted.

When the gray scale data D0-D2 is (111) at one pixel, the conversion ofthe gray scale data is performed according to the table listed in FIG.5(a). Referring to FIG. 7, on the pixel electrode 118 at that pixel, ahigh level is written throughout one field (1f). The transmittance ratioof the pixel is thus 100% corresponding to the gray scale data of (111).

When the alternating driving signal FR is at a high level, the pixelelectrode 118 is applied with the voltage in level shifted from the onewith the alternating driving signal FR at a low level. With respect toan intermediate voltage between the voltage V7, which is at a highlevel, and the voltage V0, which is at a low level, the voltage appliedto the liquid-crystal layer with the alternating driving signal FR at ahigh level is inverted in polarity from the voltage applied to theliquid-crystal layer with the alternating driving signal FR at a lowlevel. The absolute values of the voltages applied to the liquid-crystallayer are equal. This arrangement prevents a direct current componentfrom being applied to the liquid-crystal layer, thereby slowing theaging of the liquid crystal 105.

The electro-optical device of this embodiment divides the one field (1f)into the subfields Sf1-Sf7 in accordance with the voltage ratio of thegray scale characteristics, and writes a high level or a low level on asubfield by subfield basis, thereby controlling the root-mean-squarevoltage in the one field. For this reason, the data signals d1-dnsupplied to the data lines 114 are binary, i.e., either a high level(=V7) or a low level (=V0) in this embodiment. The peripheral circuits,such as driving circuits, do not need circuits for processing analogsignals, such as a high-precision digital-to-analog converter circuit oran operational amplifier. The circuit arrangement is thus substantiallysimplified, thereby reducing the overall cost of the device. Since thedata signals d1-dn supplied to the data lines 114 are binary, no displaynonuniformities occur-due to irregularities in element characteristicsand wiring resistance. The electro-optical device of this embodimentthus presents a high-quality and high-definition gray scale display.

In the above embodiment, the alternating driving signal FR islevel-shifted every field. The present invention is not limited to thismethod. For example, the alternating driving signal FR may belevel-shifted every two or more fields.

Modification (1)

In the above embodiment, the writing of the subfield needs to becompleted for a short period (1 Va) which is shorter than the shortestsubfield. The above embodiment has been discussed in connection with theeight-gray scale display. To increase the number of gray scales to 16gray scales, 64 gray scales, . . . , for example, the length of thesubfield needs to be shortened to complete the writing of each subfieldin an even shorter time.

However, the driving circuits, particularly the X shift register 1410 inthe data line driving circuit 140 runs in an operating frequency closeto its upper limit, and the number of gray scales cannot be increased inthis arrangement. A modification with improvements in this regard is nowdiscussed.

FIG. 8 is a block diagram showing the construction of the data linedriving circuit in an electro-optical device in accordance with themodification. As shown, an X shift register 1412 is identical to the Xshift register 1410 shown in FIG. 3 in that the latch pulse LP istransferred in synchronization with the clock signal CLX. The differenceof the X shift register 1412 from the X shift register 1410 is that theX shift register 1412 has half the number of stages of the X shiftregister 1410. Specifically, let p represent an integer satisfying thecondition of n=2p, and the X shift register 1412 sequentially outputslatch signals S1, S2, . . . , Sp.

In this modification, the binary signals Ds are distributed in twolines, i.e., binary signals Ds1 to odd-numbered data lines 114 andbinary signals Ds2 to even-numbered data lines 114, counted from theleft. In a first latch circuit 1422, one latch for latching the binarysignal Ds1 corresponding to the odd-numbered data line 114 and one latchfor latching the binary signal Ds2 corresponding to the even-numbereddata line 114 are arranged in pairs, and the pair of latches performlatching at the falling edge of the same latch signal.

As shown in FIG. 9, the data line driving circuit 140 allows each of thelatch signals S1, S2, S3, . . . to concurrently latch the two binarysignals Ds1 and Ds2. The required horizontal scanning period is halvedwith the frequency of the clock signal CLX in the above embodimentmaintained. The number of stages of the X shift register 1412 is reducedto “p”, which is half the number of the data lines 114, namely, “n”. Theconstruction of the X shift register 1412 can be simplified from that ofthe X shift register 1410 (see FIG. 3).

The number of stages of the X shift register 1412, half the number ofstages of the X shift register 1410, suggests that half the frequency ofthe clock signal CLX works given the same horizontal scanning period. Ifthe horizontal scanning period remains the same, power affected by theoperating frequency is reduced.

In the modification, the number of latches performing concurrentlylatching in response to the latch signal in the first latch circuit 1422is “2”, but that number may be “3” or more. In this case, the binarysignals may be distributed in lines of the corresponding number, and thenumber of stages of the X shift register 1412 is reduced to a numberthat is obtained by dividing the original number of stages by the numberof signal lines.

Modification (2)

In the preceding embodiments, the writing in each subfield is completedwithin the period (1 Va). The voltage written onto the liquid-crystallayer in each pixel is held for a period from the end of the writing tothe start of a next subfield in one subfield.

The driving circuits in the above embodiments, particularly, the dataline driving circuit 140 receives a very high-frequency clock signalCLX. The shift register typically includes a number of clocked invertersfor receiving the clock signal at the gates thereof. If viewed from thetiming signal generator circuit 200 as a source of the clock signal CLX,the X shift register 1410 (1412) works as a capacitive load.

The arrangement, which allows the clock signal CLX to be supplied duringthe above-discussed voltage hold period, consumes power in vain by thecapacitive load, thereby increasing power consumption. Anothermodification free from this disadvantage is now discussed.

In this modification, a clock signal supply control circuit 400 shown inFIG. 10 is inserted in a path of the clock signal CLX extending to the Xshift register 1410 (1412) from the timing signal generator circuit 200.The clock signal supply control circuit 400 includes an RS flipflop 402and an AND gate 404. The RS flipflop 402 receives the start pulse DY atthe set input terminal S thereof and the scanning signal Gm at the resetinput terminal R thereof. The AND gate 404 AND-gates the clock signalCLX supplied by the timing signal generator circuit 200 and the signalfrom the output terminal Q of the RS flipflop 402, and supplies theAND-gated output thereof to the X shift register 1410 (1412) in the dataline driving circuit 140.

When the start pulse DY is supplied to the clock signal supply controlcircuit 400 at the start of one subfield, the RS flipflop 402 is set,thereby transitioning an enable signal Enb output from the outputterminal Q to a high level as shown in FIG. 11. In response, the ANDgate 404 is opened, thereby starting the supply of the clock signal CLXto the X shift register 1410 (1412). In the data line driving circuit140, the first latch circuit 1420 (1422) starts sequentially latchingdata in a point at a time scanning in response to the latch pulse LPwhich is supplied immediately subsequent to the start of the supply ofthe clock signal CLX.

On the other hand, when the scanning signal Gm for selecting the lastscanning line (m-th scanning line from the top) 112 in the subfield issupplied subsequent to the start of the supply of the clock signal CLXin response to the start pulse DY, the RS flipflop 402 is reset. Theenable signal Enb output from the output terminal Q of the RS flipflop402 is driven low in level as shown in FIG. 11. In response, the ANDgate 404 is closed, and the supply of the clock signal CLX to the Xshift register 1410 (1412) is cut off. Since data for one row of pixelsintersecting the m-th scanning line 112 is latched by the first latchcircuit 1420 (1422) prior to the supply of the scanning signal Gm, thecutting of the supply of the clock signal CLX until the start of thenext subfield presents no problem at all.

With such a clock signal supply control circuit 400 arranged, the clocksignal CLX is fed to the X shift register 1410 (1412) only when theclock signal CLX is needed. Power consumed by the capacitive load isaccordingly reduced. Although a similar clock signal supply controlcircuit may be arranged for the clock signal CLY on the Y side, itsfrequency is substantially lower than the frequency of the clock signalCLX on the X side. Power consumed by the capacitive load on the Y sideis not so problematic as that on the X side.

Modification (3)

In the preceding embodiments, the voltage V0 is at a low level, and thevoltage V7 is at a high level. With this arrangement, the voltage V7 fora transmittance ratio of 100% needs to be generated separately from asingle power source. As apparent from FIG. 4(a), a root-mean-squarevalue not less than V7 results in a transmittance ratio of 100%, and ahigh-potential voltage Vcc of a power source (3 V, for example) may bedirectly used as a high level voltage without the need for separatelygenerating the voltage V7. If Vcc is defined as a high level, the use ofthe power source voltage permits a gray scale display.

In the arrangement in which the voltage Vcc is used as a high level, thevoltage V7 may be treated in the same way as the voltages V2-V6 are inthe preceding embodiments. Furthermore, one field (1f) may be dividedinto eight subfields Sf1-Sf8 having the following lengths.

Specifically, the subfield Sf1 is set to have a length of (V1/Vcc)² tothe one field (1f), the subfield Sf2 is set to have a length of(V2/Vcc)²−(V1/Vcc)² to the one field (1f), and the subfield Sf3 is setto have a length of (V3/Vcc)²−(V2/Vcc)² to the one field (1f).Similarly, the subfields are set, and finally, the subfield Sf8 is setto have a length of (Vcc/Vcc)²−(V7/Vcc)² to the one field (1f).

From among the subfields Sf1-Sf8 thus set, subfields Sf1-Sf7 aresubjected to the writing in the same way as already discussed inconnection with the first embodiment. For the new subfield Sf8, thevoltage is at the same level as the alternating driving signal FR, i.e.,at the same level as the voltage of the counter electrode 108. Duringthe subfield Sf8, the liquid-crystal layer is supplied with no voltageregardless of the gray scale data. In other words, to attain atransmittance ratio of 100%, it is not necessary to continuously keepthe liquid-crystal layer turned on throughout one field (1f).

Modification (4)

In the preceding embodiments, voltage is applied to turn on the pixelfor a period in response to the gray scale data. Specifically, as shownin FIG. 7, to apply the root-mean-square voltage V1 corresponding to thegray scale data (001) to the pixel, an on voltage is applied during thesubfield Sf1, and to apply the root-mean-square voltage V3 correspondingto the gray scale data (011), the on voltage is applied during thesubfields of Sf1-Sf3, and to apply the root-mean-square voltage V6corresponding to the gray scale data (110), the on voltage is appliedduring the subfields of Sf1-Sf6. In this way, one field is divided intosubfields, the number of which corresponds to the number of gray scalesto be displayed. The division of the field into the subfields is notlimited to this method. For example, the following method iscontemplated.

FIGS. 12(a) and 12(b) are truth tables that represent the function ofthe data converter circuit 300 of an electro-optical device inaccordance with a modification. FIG. 13 is a timing diagram showing theoperation of the electro-optical device of this modification.

In this modification, one field is divided into four subfields, andon/off driving performed in each of four subfields Sf0-Sf3 according totruth tables shown in FIGS. 12(a) or 12(b). In this way, an eight-grayscale display is provided in response to three-bit gray scale data. Thetime sharing of the subfields in this modification is partly differentfrom that in the preceding embodiments. Specifically, as itemized ina-d, the subfields have time lengths that present root-mean-squarevoltages having different weights to the pixels.

a. The subfield Sf0 has a time length long enough to supply theliquid-crystal layer with a root-mean-square voltage corresponding tothe threshold VHT1 of the liquid crystal as shown in FIG. 4(a).

b. The subfield Sf1 has a time length long enough to supply the pixelwith a root-mean-square voltage corresponding to a weight “1”.

c. The subfield Sf2 has a time length long enough to supply the pixelwith a root-mean-square voltage corresponding to a weight “2”.

d. The subfield Sf3 has a time length long enough to supply the pixelwith a root-mean-square voltage corresponding to a weight “4”.

As apparent from the above discussion, to apply a root-mean-squarevoltage to the liquid-crystal layer, the pixel is set to an ON stateduring the subfield Sf0. As shown in FIGS. 12(a) and 12(b), in the grayscale data other than (000), the binary signals Ds for the subfield Sf0have the level to turn on the pixels.

Referring to FIG. 13, the voltage applied to each pixel in accordancewith the gray scale data is discussed. When the gray scale data is(001), the voltage to turn on the pixel is applied during the subfieldsSf0 and Sf1, and as a result, the root-mean-square voltage applied tothe liquid-crystal layer becomes V1 during one field. Similarly, whenthe gray scale data is (010), the voltage to turn the pixel is appliedduring the subfields Sf0 and Sf2, and as a result, the root-mean-squarevoltage applied to the liquid-crystal layer becomes V2 during one field.Also in the remaining gray scale data, truth tables listed in FIGS.12(a) and 12(b) are used to determine whether to apply the voltage toturn on or off the pixel in each subfield. As a result, theliquid-crystal layer is applied with the root-mean-square voltageresponsive to the gray scale data.

This modification also provides the same advantage as that of thepreceding embodiments. A smaller number of subfields work in thismodification when the number of gray scales remains unchanged from thatof the preceding embodiments. Since a count of data writing in one fieldis thus reduced, power consumption is reduced.

The number and time lengths of subfields are determined considering thenumber of gray scales to be displayed, and voltage/transmittancecharacteristics of the pixel in an electro-optical device in use, andare not limited to those already discussed in connection with thepreceding embodiments. In this modification, the subfield Sf0 has a timelength long enough to supply the pixel with a voltage as high as thethreshold voltage VTH1 of the liquid crystal. Such a subfield is not arequirement. It is important that the number of and time lengths of thesubfields are determined so that a root-mean-square voltage responsiveto a gray scale to be displayed is applied to the pixel within a rangeof the voltage VTH1 through V7 as shown in FIG. 4(a). The voltageapplied to the pixel electrode may be the power source voltage Vcc as ahigh level as already discussed in connection with the modification (3).

In this modification, the subfield Sf0 for applying the root-mean-squarevoltage VTH1 to the pixels is arranged at the first portion of eachfield. The position of this subfield may be located anywhere within eachfield. In this modification, only a single subfield Sf0 is arranged as asubfield that can apply the root-mean-square voltage VTH1 to the pixel.The present invention is not limited to this method. Alternatively, thefollowing method may be employed. Specifically, rather than using thesubfield Sf0, predetermined periods of time are inserted between thesubfields Sf1-Sf3, and the sum of the predetermined periods may be atime length which allows the root-mean-square voltage VTH1 to be appliedto the pixel. In other words, the subfield Sf0 having a time length thatallows the root-mean-square voltage VTH1 to be applied is split into aplurality of segments, and these segments are inserted betweensubsequent subfields. It is important that the time length of the onefield except subfields Sf1-Sf3 is a time length capable of applying theroot-mean-square voltage VTH1 to the pixel.

General Construction of the Liquid-Crystal Device

The construction of the electro-optical devices in accordance with theabove embodiment and modifications are now discussed, referring to FIG.14 and FIG. 15. FIG. 14 is a plan view of the electro-optical device 100and FIG. 15 is a sectional view of the electro-optical device 100 takenalong line XV-XV′ in FIG. 14.

As shown, the electro-optical device 100 includes the element substrate101 having the pixel electrodes 118 formed thereon, and the countersubstrate 102 having the counter electrode 108 formed thereon. Theelement substrate 101 and the counter substrate 102 are glued onto eachother with a sealing member 104 interposed therebetween, with a gapmaintained therebetween. The liquid crystal 105 as an electro-opticalmaterial is encapsulated in the gap. The sealing member 104 has acutout, through which the liquid crystal 105 is introduced, and then,the cutout is closed by an encapsulating material. The cutout is notshown in FIG. 14 and FIG. 15.

When the element substrate 101 is fabricated of a semiconductorsubstrate, the substrate is opaque. The pixel electrode 118 is thusformed of a reflective metal such as aluminum, and the electro-opticaldevice 100 is thus of a reflective type. In contrast, the countersubstrate 102, fabricated of glass, is transparent. The elementsubstrate 101 may be fabricated of a transparent insulator substratesuch as glass. With the element substrate 101 fabricated of an insulatorsubstrate, a reflective type display device is provided when the pixelelectrode is formed of a reflective material. When the pixel electrodeis formed of a material other than this, a transmissive type displaydevice is provided.

A light-shielding layer 106 is arranged on the element substrate 101internal to the sealing member 104 but external to a display area 101 a.The scanning line driving circuit 130 is formed in a region 130 a of thearea where the light-shielding layer 106 is formed. The data linedriving circuit 140 is arranged on a region 140 a. The light-shieldinglayer 106 therefore prevents light from being incident on the drivingcircuits formed in these regions. The light-shielding layer 106 and thecounter electrode 108 are supplied with the alternating driving signalFR. The area having the light-shielding layer 106, having substantiallyno voltage with respect to the liquid-crystal layer, provides the samedisplay state as that of the pixel electrode 118 with no voltageapplied.

A region 107 on the element substrate 101, external to the region 140 aof the data line driving circuit 140, and separated by the sealingmember 104, has a plurality of terminals to receive control signals anda power source voltage from outside.

On the other hand, the counter electrode 108 on the counter substrate102 is electrically connected to the light-shielding layer 106, andinterconnect terminals arranged on the element substrate 101 viaconductor members (not shown) arranged at least one of the four cornersof a substrate attachment portion. Specifically, the alternating drivingsignal FR is applied to the light-shielding layer 106 via theinterconnect terminals arranged on the element substrate 101 and then tothe counter electrode 108 via the conductor members.

Depending on the application of the electro-optical device 100, a colorfilter patterned in stripe, mosaic, or triangles is first mounted on thecounter substrate 102 if the electro-optical device 100 is of a directviewing type. Second, a light-shielding layer (black matrix) made of,for example, metal material or resin is mounted on the counter substrate102. When the electro-optical device 100 is applied for lightmodulation, such as a light valve of a projector as discussed later, nocolor filter is arranged. In a direct viewing type, as necessary, afront light is arranged to illuminate the electro-optical device 100from the counter substrate 102. An alignment layer (not shown),subjected to a rubbing process in a predetermined direction, is arrangedon the electrode formation surfaces of the element substrate 101 and thecounter substrate 102. The alignment direction of liquid-crystalmolecules with no voltage applied is thus defined. Furthermore, apolarizer (not shown) compatible with the alignment direction isarranged on the element substrate 101. If a polymer dispersed liquidcrystal consisting of a mixture of a liquid crystal and polymer is usedas the liquid crystal 105, the above-mentioned alignment layer and thepolarizer are dispensed with. With a high utilization of light, theelectro-optical device 100 thus provides advantages, such as increasedluminance, and reduced power consumption.

In the preceding embodiments, the element substrate 101 forming theelectro-optical device is a semiconductor substrate, and the transistors116 respectively connected to the pixel electrodes 118 and elements usedin the driving circuits are MOSFET transistors. The present invention isnot limited to this type. For example, the element substrate 101 may befabricated of an amorphous substrate such as of glass or quartz, andthen a semiconductor thin film may be deposited thereon to form athin-film transistor (TFT). With the TFT, a transparent substrate may beused as the element substrate 101.

Employed as the liquid crystal, besides the TN type, may be an STN(Super Twisted Nematic) type having 180 degree or more twistedalignment, a BTN (Bistable Twisted Nematic) type, a ferroelectric typeemploying a bistable twisted nematic liquid crystal having memory, apolymer dispersed type, or a guest-host type in which a dye (guest)having anisotropy in the absorption of visible light in the minor axisand the major axis of molecules is dissolved in a liquid crystal (host)having a predetermined molecular arrangement and the dye molecules andthe liquid-crystal molecules are arranged in parallel.

Perpendicular alignment (homeotropic alignment) may be arranged in whichthe liquid-crystal molecules are perpendicularly aligned with respect tothe two substrates with no voltage applied, and aligned in parallel tothe two substrates with a voltage applied. On the other hand, parallel(planar) alignment (homogeneous alignment) may be arranged in which theliquid-crystal molecules are aligned in parallel to the two substrateswith no voltage applied, and are perpendicularly aligned to the twosubstrates with a voltage applied. Rather than arranging the counterelectrode on the counter substrate, the counter electrode may bearranged on the element substrate in a manner such that pixel electrodesand the counter electrode are interdigitally spaced with a gapmaintained therebetween. With this arrangement, the liquid crystalmolecules are aligned in parallel with the two substrates, and thealignment direction of the molecules varies in response to a parallelelectric field taking place between the electrodes. As long as thedriving method of the present invention is applicable, a variety ofliquid crystals and a variety of alignment methods are acceptable.

Besides the liquid-crystal device, the present invention is applied to adiversity of electro-optical devices including electroluminescences(EL), digital micro-mirror devices (DMD), and devices which present adisplay using the electro-optical effect based on fluorescence by plasmaemission or electron emission. In this case, the electro-opticalmaterials may include EL, a mirror device, gas, fluorescent materials,etc. When the EL is used as an electro-optical material, the EL isinterposed between the pixel electrode and the counter electrode of thetransparent, electrically conductive layer, and the counter electrode isthus dispensed with. The present invention is thus applicable toelectro-optical devices having a construction similar to the onesdiscussed above, and in particular, to all electro-optical devices thatpresent a gray scale display using pixels that provides binarypresentation of on and off.

Electronic Equipment

Several specific examples of electronic equipment using theabove-described liquid-crystal device are now discussed.

Electronic Equipment 1: Projector

Discussed first is a projector which uses the electro-optical device ofeach of the above embodiments as a light valve. FIG. 16 is a plan viewshowing the projector. As shown, the projector 1100 includes a polarizerillumination unit 1110 along a system optical axis PL. In the polarizerillumination unit 1110, a light beam from a lamp 1112 is reflected andsubstantially collimated by a reflector 1114, and enters a firstintegrator lens 1120. The output light beam from the lamp 1112 is splitinto a plurality of intermediate light beams. The split intermediatelight beams are converted into polarized light beams of one type havinga substantially uniform polarization (s-polarized light beams) through apolarizer assembly 1130 having a second integrator lens on the lightincident side thereof, and are then output from the polarizerillumination unit 1110.

The s-polarized light beams exiting from the polarizer illumination unit1110 is reflected from the s-polarized light beam reflecting surface1141 of a polarizing beam splitter 1140. The blue light beam (B) of thereflected light beams is reflected from the blue-light reflecting layerof a dichroic mirror 1151, and is then modulated by a reflective-typeelectro-optical device 100B. The red light beam (R) of the light beamstransmitted through the blue-light reflecting layer is reflected from ared-light reflecting layer of the dichroic mirror 1152, and is thenmodulated by a reflective-type electro-optical device 100R. The greenlight beam (G) of the light beams transmitted through the blue-lightreflecting layer of the dichroic mirror 1151 is transmitted through ared-light reflecting layer of a dichroic mirror 1152, and is thenmodulated by the a reflective-type electro-optical device 100G.

The red, green, and glue light beams respectively color-modulated by theelectro-optical devices 100R, 100G, and 100B are synthesized by thedichroic mirrors 1152 and 1151, and the polarizing beam splitter 1140,and then projected onto a screen 1170 through a projection opticalsystem 1160. The electro-optical devices 100R, 100G, and 100B need nocolor filter because these devices receive the three primary colors ofR, G, and B.

Although this embodiment uses the reflective-type electro-opticaldevice, the projector may employ a transmissive-type electro-opticaldevice.

Electronic Equipment 2: Mobile Computer

Discussed here is a mobile computer incorporating the above-referencedelectro-optical device. FIG. 17 is a perspective view of theconstruction of the mobile computer. The computer 1200 includes a mainunit 1204 having a keyboard 1202, and a display unit 1206. The displayunit 1206 is composed of the above-referenced electro-optical device 100with a front light attached on the front thereof.

In this embodiment, the electro-optical device 100 is of a reflectivedirect-viewing type, and preferably, irregularity is formed on the pixelelectrode 118 so that a light beam reflected therefrom is scattered invarious directions.

Electronic Equipment (3): Portable Telephone

Discussed next is a portable telephone incorporating theabove-referenced electro-optical device. FIG. 18 is a perspective viewof the portable telephone. As shown, the portable telephone 1300includes a plurality of control buttons 1302, an earpiece 1304, amouthpiece 1306, and the electro-optical device 100. The electro-opticaldevice 100 is provided with a front light on the front thereof asnecessary. Since the electro-optical device 100 is of a reflectivedirect-viewing type in this embodiment again, irregularity is preferablyformed on the pixel electrode 118.

Besides the electronic equipment described with reference to FIG. 16through FIG. 18, the electronic equipment of the present invention maybe any of a diversity of electronic equipment including a liquid-crystaldisplay television, a viewfinder type or direct-monitoring type videocassette recorder, a car navigation system, a pager, an electronicpocketbook, an electronic tabletop calculator, a word processor, aworkstation, a video phone, a POS terminal, and an apparatus having atouch panel. These pieces of electronic equipment may incorporate theelectronic devices of the above embodiment and modifications.

In accordance with the present invention, as described above, the signalapplied to the data line is binarized, and a high-quality gray scaledisplay thus results.

INDUSTRIAL APPLICABILITY

The present invention provides an optimum driving method in anelectro-optical device that performs gray scale display control usingpulse width modulation, and is appropriate for use as a display devicehaving excellent characteristics in electronic equipment.

1. A driving method for driving an electro-optical device having a pixel with a pixel electrode arranged corresponding to an intersection where a scanning line and a data line cross, the pixel having a switching element, an electro-optical material, a storage capacitor and a counter electrode arranged to be opposed to the pixel electrode, in a plurality of driving fields to display an image with gray scale, the method comprising the steps of: dividing each driving field into a plurality of subfields; supplying a scanning signal to the scanning line in each subfield; and feeding a binary signal for controlling the pixel to be in an ON state or an OFF state from the data line through the switching element to the electro-optical material and the storage capacitor, the storage capacitor holding the binary signal; and the binary signal setting the pixel to the ON state or the OFF state so that a ratio of a period of voltage application time to set the pixels to the ON state to a period of voltage application time to set the pixels to the OFF state in each driving field is responsive to the gray scale level of the pixel, the binary signal being shifted in response to a level of voltage applied to the counter electrode.
 2. The driving method for driving an electro-optical device according to claim 1, the subfields divided from one driving field having time lengths long enough so as to feed a different root-mean-square voltage to each subfield.
 3. A driving circuit of an electro-optical device for driving pixels in a plurality of driving fields, comprising: a data line, a scanning line, a pixel with a pixel electrode arranged corresponding to an intersection where the scanning line and the data line cross, and having a switching element, an electro-optical material, a storage capacitor, and a counter electrode arranged to be disposed opposed to the pixel electrode; a scanning line driving circuit that supplies the scanning line with a scanning signal that turns on the switching element in each of a plurality of subfields divided from one driving field; and a data line driving circuit that supplies the data line with a binary signal controlling the pixel to be set to an ON state or an OFF state from the data line through the switching element to an electro-optical material and the storage capacitor, the storage capacitor holding the binary signal; and the binary signal setting the pixel to the ON state or to the OFF state so that a ratio of a period of voltage application time to set the pixels to the ON state to a period of voltage application time to set the pixels to the OFF state in each driving field is responsive to a gray scale level of the pixel, the binary signal being shifted in response to a level of voltage applied to the counter electrode.
 4. The driving circuit of an electro-optical device according to claim 3, the data line driving circuit further comprising: a shift register that sequentially shifts and outputs a latch pulse signal, supplied at the start of a horizontal scanning period, in response to a clock signal; a first latch circuit that sequentially latches the binary signal in response to the shifted signal provided by the shift register; and a second latch circuit which latches the binary signal, latched by the first latch circuit, in response to the latch pulse signal while simultaneously outputting the latched binary signals to corresponding data lines.
 5. The driving circuit of an electro-optical device according to claim 4, the first latch circuit simultaneously latching the binary signals, which are branched into a plurality of lines from a single line, in response to the shifted signal provided by the shift register.
 6. The driving circuit of an electro-optical device according to claim 4, comprising a clock signal supply control circuit, the clock signal supply control circuit stopping supply of the clock signal to the shift register after the scanning line driving circuit supplies all scanning lines with the scanning signal in one subfield, and restarting the supply of the clock signal at a start of a subsequent subfield.
 7. An electro-optical device, comprising: a data line, a scanning line, a pixel having a pixel electrode corresponding to an intersection where the scanning line and the data line cross, a switching element, a storage capacitor, and a counter electrode arranged to be opposed to the pixel electrode; a scanning line driving circuit that supplies the scanning line with a scanning signal that turns on the switching element in each of a plurality of subfields divided from one driving field of a plurality of driving fields; and a data line driving circuit that supplies the data line with a binary signal controlling the pixel to be in an ON state or an OFF state from the data line through the switching element to an electro-optical material and the storage capacitor, the storage capacitor holding the binary signal; the binary signal setting the pixel to an ON state or to an OFF state so that a ratio of a period of voltage application time to set the pixel to the ON state to a period of voltage application time to set the pixel to the OFF state in each driving field is responsive to a gray scale level of the pixel, the binary signal being shifted in level in response to a level of a voltage applied to the counter electrode.
 8. The electro-optical device according to claim 7, an element substrate on which the pixel electrode and the switching element are formed being fabricated of a semiconductor substrate, and the scanning line driving circuit and the data line driving circuit being produced on the element substrate, and the pixel electrode having reflectivity.
 9. Electronic equipment comprising the electro-optical device according to claim
 7. 